Research Article
FPGA Based Implementation of FFT Processor Using Different Architectures
Debalina Ghosh1*, Depanwita Debnath2 and Dr. Amlan Chakrabarti31Microelectronics and VLSI Design Techno India, Salt Lake Kolkata, India
2Electronics and Communication Engineering Techno India, Salt Lake Kolkata, India
3A.K.Choudhury, School of Information Technology University of Calcutta Kolkata, India
- *Corresponding Author:
- Debalina Ghosh
Microelectronics and VLSI Design Techno India, Salt Lake Kolkata, India
E-mail: debolina1512@gmail.com
Abstract
The Fast Fourier Transform (FFT) is an efficient algorithm for computing the Discrete Fourier Transform (DFT) and requires less number of computations than that of direct evaluation of DFT. It has several applications in signal processing. Because of the complexity of the processing algorithm of FFT, recently various FFT algorithms have been proposed to meet real-time processing requirements and to reduce hardware complexity over the last decades. This is in two directions. One related to the algorithmic point of view and the other based on ASIC architecture. The last one was pushed by VLSI technology evolution. In this work, we present three different architectures of FFT processor to perform 1024 point FFT analysis. The designs have been simulated and its FPGA based implementation has been verified successfully using Xilinx ISE 11.1 tool using VHDL. There are also comparative studies among those architectures. The objective of this work was to get an area & time efficient architecture that could be used as a coprocessor with built in all resources necessary for an embedded DSP application.
